Microwave power amplifiers using discrete (unpackaged) wide bandgap transistors can be realised in a hybrid arrangement, either using a single transistor or using several such transistors combined (in parallel) and assembled with specific separate passive electronic components to achieve a prescribed level of performance. This hybrid microwave integrated circuit (MIC) realisation is often preferred to an integrated solution (such as a microwave monolithic integrated circuit or MMIC), as it can lead to much improved performance through the use of higher “Q” external embedding electronic components. A requirement of the MIC arrangement is that the discrete transistors are connected to input and output matching networks or components through the use of many bond wires. The output of each transistor comprises a large number of intrinsic parallel feeds, and therefore has low impedance (when compared with a low-power transistor), while the input comprises a large number of gates, and therefore has relatively high capacitance (when compared with a low-power transistor). It can therefore be difficult to provide a suitable impedance match between the transistor and its embedding circuits which provides good power transfer across a required band of frequencies. Such a match requires the application of prescribed inductive and capacitive reactances.
Bond wires in MIC devices are used to connect together individual discrete components and are typically short lengths (say 50-500 μm) of thin (say 25 μm diameter), high-conductivity (often gold or aluminium) wires that are assembled using conventional wire-bonding equipment. These bond wires have an inductive reactance that increases with operating frequency (XL=ωL, where XL is the inductive reactance, ω is the frequency and L is the length of the bond wire) and which is critically dependent upon the length and orientation of the wire.
This, however, results in a problem: designs which use bond wires to form part of the inductance of an impedance transformation are susceptible to performance variation from bond wire manufacturing production tolerance. In particular, the inductance provided by a bond wire is critically determined by its length and shape, and even slight variations in bond wire length or orientation can lead to changes in inductance, especially at high frequencies. For example, variations in bond wire length that may not present a particular problem at 2 GHz become rather more problematic at 20 GHz, where its reactance is a factor of 10 higher for the same length of wire.
The bond wire inductance, being part of the overall hybrid amplifier circuit, needs to be accurately controlled to ensure repeatable and high-yielding circuit performance. Some consistency and control may be achieved through the use of automated wire bonding techniques, but this is not always possible for low-volume production runs, and the wire lengths are still subject to a specific manufacturing tolerance.
The main problem therefore is how to overcome the inherent performance variation (and consequent limitation on manufacturing yield) from an MIC power amplifier which uses bond wires with potentially randomly or systemic varying dimensions within the important embedding matching networks. In other words, how to reduce significantly the sensitivity of the performance of such an amplifier to manufacturing variations in the bond wires used in the amplifier matching networks.
In addition to this main problem, there is a need to implement matching networks that can accommodate the low output impedance and high input reactance of wide bandgap transistors (although the same problem can also exist with other conventional FET devices). This can be achieved through the use of external “lumped” shunt capacitive matching elements (chip capacitors) as impedance transformers, but these require close attention to the effect of extrinsic bond wire inductance. An example of such a matching network is known from EP2197030, which discloses a high frequency semiconductor device taking the form of a field effect transistor (FET) with multiple parallel inputs and multiple parallel outputs, each realised by a plurality of bond wires.
Another problem is that lumped designs which use separate inductors (bond wires) and chip capacitors to implement an impedance transformation have an inherent bandwidth limitation when compared with the use of a distributed network, unless the number of capacitive and inductive stages is increased.